1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to techniques for filling contact openings and vias with copper, and creating copper interconnections and lines.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
However, reducing the size, or scale, of the components of a typical transistor also requires reducing the size and cross-sectional dimensions of electrical interconnects contacting active areas, such as N+(P+) source/drain regions and a doped-polycrystalline silicon (doped-polysilicon or doped-poly) gate conductor, and the like. As the size and cross-sectional dimensions of electrical interconnects get smaller, resistance increases and electromigration increases. Increased resistance and electromigration are undesirable for a number of reasons. For example, increased resistance may reduce device drive current and source/drain current through the device, and may also adversely affect the overall speed and operation of the transistor. Additionally, electromigration effects in aluminum (Al) interconnects, where electrical currents actually carry Al atoms along with the current, causing them to electromigrate, may lead to degradation of the Al interconnects, further increased resistance, and even disconnection and/or delamination of the Al interconnects.
The ideal interconnect conductor for semiconductor circuitry will be inexpensive, easily patterned, have low resistivity, and high resistance to corrosion, electromigration, and stress migration. Aluminum (Al) is most often used for interconnects in contemporary semiconductor fabrication processes, primarily because aluminum (Al) is inexpensive and easier to etch than, for example, copper (Cu). However, because aluminum (Al) has poor electromigration characteristics and high susceptibility to stress migration, it is typical to alloy aluminum (Al) with other metals.
As discussed above, as semiconductor device geometries shrink and clock speeds increase, it becomes increasingly desirable to reduce the resistance of the circuit metallization. The one criterion that is most seriously compromised by the use of aluminum (Al) for interconnects is that of conductivity. This is because the three metals with lower resistivities (aluminum has a resistivity of 2.824×10−6 ohms-cm at 20° C.), namely, silver (Ag) with a resistivity of 1.59×10−6 ohms-cm (at 20° C.), copper (Cu) with a resistivity of 1.73×106 ohms-cm (at 20° C.), and gold (Au) with a resistivity of 2.44×106 ohms-cm (at 20° C.), fall short in other significant criteria Silver (Ag), for example, is relatively expensive and corrodes easily, and gold (Au) is very costly and difficult to etch. Copper (Cu), with a resistivity nearly on par with silver (Ag), immunity from electromigration, high ductility and high melting point (1083° C. for copper vs. 660° C. for aluminum), fills most criteria admirably. However, copper (Cu) is difficult to etch in a semiconductor environment. As a result of the difficulty in etching copper (Cu), an alternative approach to forming vias and metal lines is used. The damascene approach, both single-damascene and dual-damascene, consisting of etching openings such as trenches in the dielectric for lines and/or vias and creating in-laid metal patterns, is the leading contender for fabrication of sub-0.25 micron (sub-0.25 μL) design rule copper-metallized circuits.
The conventional dual-damascene copper (Cu) process flow combines intermetal via connection formation with copper (Cu) trench-fill formation by etching a more complex pattern before the formation of a barrier metal layer and copper (Cu) seed layer and before the copper (Cu) trench-fill. The trenches, which define the wider metal lines, are typically etched first, and the vias, which define the narrower interlayer metal interconnects, are typically etched last, in what is known as a trench-first-via-last (TFVL) approach. Overall, the conventional dual-damascene copper (Cu) process flow significantly reduces the number of processing steps as compared to the conventional single-damascene copper (Cu) process flow, and is a preferred method of achieving copper-metallization.
The trench-first-via-last (TFVL) approach is also a preferred process flow, since the trench-first-via-last (TFVL) approach is relatively easier to carry out than an alternative via-first-trench-last (VFTL) approach. However, during the conventional trench-first-via-last (TFVL) approach, the photolithographic patterning for the vias faces the problem that, once the openings for the trenches are formed, the photoresist has varying thickness across the surface of the workpiece.
As shown in FIG. 1, for example, a photoresist layer 150 may have a thickness δ above a trench opening 110, whereas the photoresist layer 150 may have a thickness Δ above an upper portion of a via opening 115. The trench opening 110 and the upper portion of the via opening 115 may both be formed at the same time and may both have a depth τ that may be in a range of approximately 2000 Å-6000 Å, for example. The thickness Δ of the photoresist layer 150 above the trench opening 110 may be about 2.5 times the depth τ of the trench opening 110. However, the thickness Δ of the photoresist layer 150 above the upper portion of the via opening 115 may be about 3.5 times the depth τ of the upper portion of the via opening 115.
The trench opening 110 and the upper portion of the via opening 15 are both formed in a dielectric layer 120. The dielectric layer 120 may be formed above an optional hard mask etch stop layer 130. The optional hard mask etch stop layer 130 may be formed above a copper wire or structure layer 125 adjacent a lower dielectric layer 105. The copper wire or structure layer 125 and the lower dielectric layer 105 may be formed above a structure layer 100 such as a semiconducting substrate.
The trench opening 110 may have a width Ω that may be in a range of approximately 10000 Å-50000 Å, for example. The upper portion of the via opening 115 is typically narrower than the trench opening 110, by a factor in a range of about 8-50. The upper portion of the via opening 115 may have a width Ω that may be in a range of approximately 1000 Å-6250 Å, for example.
The greater width Ω of the trench opening 110, as compared to the narrower width co of the upper portion of the via opening 115, may lead to the variation in the thickness of the photoresist layer 150, in the conventional trench-first-via-last (TFVL) approach. As shown in FIG. 1, the thickness δ of the photoresist layer 150 above the trench opening 110 may be about 70% of the thickness Δ of the photoresist layer 150 above the upper portion of the via opening 115. This variation in the thickness of the photoresist layer 150 may lead to increased problems in subsequent photolithography processes, such as processes that pattern and define further via openings. The variation in the thicknesses of the photoresist layer 150 may lead to different optimal focus settings for various patterned structures. The region of common depth of focus (DOF) is reduced, often to the point where there may be almost no common depth of focus (DOF) left remaining for all the various different features and structures that need to be patterned. This may lead to missing vias, since the photoresist layer 150 may not be sufficiently exposed, due to the lack of a common depth of focus (DOF) because of variation in the thicknesses of the photoresist layer 150, as shown in FIG. 1.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.